entity pipeline_cu_to_alu is
  port(
    DATA_IN     : in std_logic_vector(3 downto 0);
    CLK_i       : in std_logic;
    DATA_OUT    : out std_logic_vector(3 downto 0)
  );
end pipeline_cu_to_alu;

architecture structural of pipeline_cu_to_alu is

  component reg_cu_to_alu
    port(
      D_i     : in std_logic_vector(3 downto 0);
      CLK_i   : in std_logic;
      Q_o     : out std_logic_vector(3 downto 0) );
  end component;

  signal data_1: std_logic_vector(3 downto 0);
  signal data_2: std_logic_vector(3 downto 0);
  signal data_3: std_logic_vector(3 downto 0);
  signal data_4: std_logic_vector(3 downto 0);

begin
	U1 : reg_cu_to_alu port map( 
		D_i   => DATA_IN,
		CLK_i => CLK_i,
		Q_o   => data_1 );
	U2 : reg_cu_to_alu port map( 
		D_i   => data_1,
		CLK_i => CLK_i,
		Q_o   => data_2 );
	U3 : reg_cu_to_alu port map( 
		D_i   => data_2,
		CLK_i => CLK_i,
		Q_o   => data_3 );
	U4 : reg_cu_to_alu port map( 
		D_i   => data_3,
		CLK_i => CLK_i,
		Q_o   => data_4 );
	U5 : reg_cu_to_alu port map( 
		D_i   => data_4,
		CLK_i => CLK_i,
		Q_o   => DATA_OUT );
end structural;
